Multi-stage switching networks are gaining acceptance as a means for interconnecting multiple devices within modern digital computing systems. In particular, in parallel systems it is common to use a multi-staged switching network to interconnect n system elements, where n can be several or thousands of processors or combinations of processors and other system elements. However, most state-of-the-art processors are designed to function as uniprocessors and do not implement the functions normally required to function effectively as multi-processors. The problem becomes one of how to effectively adapt uniprocessor personal computer and workstation systems to function in a multi-processor envoironment.
As the field of parallel processing advances, it becomes important to leverage off of existing low cost, off-the-shelf uniprocessors. This will enable cost effective and timely parallel products to be available at the marketplace. What is required to accomplish this is an efficient way to convert existing uniprocessors to function as parallel processors with minimal complexity and cost. This will enable customers to use idle processors that they already own more efficently and to add to the parallel system in a modularly growable fashion. Standard processor busses, such as the Microchannel, usually permit only small numbers (usually up to 8) devices to communicate before the bus exceeds its technology limits. In contrast to this, it is desirable to interconnect thousands of processors together as a parallel system. Certainly the interconnection mechanism for parallel systems cannot be the standard processor busses.
The state-of-the-art interconnection approaches have centered around multi-drop busses, which have many short comings, the primary of which is limited performance and expansion. The problem exists in bus-based processors that there is an ever increasing need for better I/O bus performance and the attachment of more I/O options. This is in direct conflict with the nature of a multi-drop bus technology, which loses performance as more and I/O options are added as taps to the bus. In general, standard bus architectures such as the MicroChannel (IBM Trademark) have selected a performance goal and thus limited the number of I/O taps permissable at that performance level. In the case of the MicroChannel the result is that 8 taps is the maximum number of allowable bus taps to permit bus operations to occur at 200 ns cycle times. As a result, bus-based system users are beginning to find that the I/O capability is not sufficient to meet their needs. For years people having been looking for means of increasing the I/O capability of bus-based systems.
Bus-based system performance is limited because only one user can have access to the bus at any given time. The expandability is limited because of the electrical characteristics of the multi-drop bus including drive capability, noise and reflections. A bus must be used internally for a Personal Computer (PC) or workstation, and cannot be extended outside of the packaging enclosure for the purpose of expanding the PC's or workstation's ability to increase it's I/O capability or to communicate directly with other PCs or workstations. Instead, an expansion card must be used internal to the PC or workstation and inserted into a card slot to interface with the internal bus and to provide a different interface for external expansion.
The present invention provides a means of using each bus-based machine as one node of a many noded parallel system. This is accomplished in either of two ways: 1) By interconnecting multiple PCs or workstations through an expansion card in each PC or workstation which connects to a high speed switching network and enables the individual bus-based systems to communicate with low-latency and interact as a parallel system. This allows for use of investment, yet it overcomes all the limitations placed upon a single bus-based architecture. 2) By interconnecting multiple bus-based cards by an active switch-based planar apparatus which adapts the existing bus interface to allow each card or sets of multiple cards to be interconnected via a high speed switching network . This allows the reuse of investment in expansion cards, yet it leads to a compact and low cost parallel system, while overcoming all the limitations placed upon a single bus-based architecture.
Thus, the present invention can be used to in either of two ways to expand either the computer I/O capability or to improve performance through parallel operation of multiple PCs or workstations being clustered together via a parallel, high speed network.
The state-of-the-art interconnection solutions for multiple PCs and workstations involve serial, high-latency Token Ring and Ethernet connections. However, they do not provide the parallel characteristics and low-latency concepts required for modern interconnect systems. The characteristics that are required include the ability to dynamically and quickly establish and break element interconnections, to do it cheaply and easily in one chip, to have expandability to many thousands of elements, to permit any length, non-calibrated interconnection wire lengths, to solve the distributed clocking problems and allow future frequency increases, and to permit parallel establishment and data transmittal over N switching paths simultaneously.
The distributed and fully parallel switch utilized herein to provide the required interconnect properties is the ALLNODE Switch (Asynchronous, Low Latency, inter-NODE switch), which is disclosed in U.S. Ser. No. 07/677,543 and adapted by the present invention to perform the switching of converted bus interfaces at low latencies and high bandwidths. The ALLNODE switch provides a circuit switching capability at high bandwidths, and includes distributed switch path connection set-up and tear-down controls individually within each switch--thus providing parallel set-up, low latency, and elimination of central point failures. We will further describe in the detailed description a way whereby the ALLNODE switch and the present invention can be used to solve the bus-based processor interconnection problem effectively.
Amongst the most commonly used networks for digital communication between processors are the Ethernet or Token Ring LAN networks. "Ethernet: Distributed Packet Switching for Local Computer Networks" Communication of the ACM, July 1976, Vol.19, No. 7, pp 393-404; and "Token-Ring Local Area Networks and Their Performance", W. Bux, Proceedings of the IEEE, Vol. 77, No.2, February 1989, pp 238-256; are representative articles which describe this kind of network, which provide a serial shared medium used by one node at a time to send a message to another node or nodes. The present invention is a replacement for this the Ethernet and Token-Ring networks that supports a parallel medium capable of multiple simultaneous transfers. U.S. Pat. No. 4,803,485--LAN COMMUNICATION SYSTEM, represents one LAN approach which use of the present inventions would replace. This patent describes a medium conversion adapter similar to the present invention, but for adapting various bus protocols to a communication system having multiple transmission media segments in a ring configuration, like a token ring or LAN. The present invention differs in that it adapts multiple transmission segments in an unbuffered multi-stage parallel transfer configuration, that gets latencies in the sub-microsecond range, rather than in the millisecond range of LAN's. This differences will be of value in the future.